The trend in modern microelectronic devices is to minimize device dimension in order to reduce unit cost per function and to improve device performance. However, as a device scaled from one micron down to submicron or even down to deep-submicron scale, it may suffer more stringent problems. The problems, such as hot carrier effects and punchthrough effects are two of the major constraints in CMOS transistor scaling. Further, the accumulated aberration might occur after several lithography processes during fabrication of the scaled device structure. One strategy to avoid such issues is to reduce the mask count as much as possible.
Another critical issue accompanying with the feature size of MOSFET scale down and degrading significantly the device performance is the electrostatic discharge (ESD). The lightly doped drain (LDD) is commonly used to protect hot carrier induced degradation in MOS devices with gate length in submicron order. However, it is known to have poor ESD property for the transistors with LDD structure. The ESD is easily conducted through the input/output and power lead connections into the internal devices to destroy the devices. For example, as junction depth becomes shallower, the properties of integrated circuits are easily deteriorated by the human body. The high voltage can be accidentally applied to the pins of the IC package by a person while handling, causing the breakdown of the gate oxide of the devices. Thus, it is imperative that a built-in preventive ESD circuitry is formed simultaneously with the functional transistors. Fukuda, et al., in the reference "by Fukuda, et al., EOS/ESD Symp. p. 76 (1996)", give a comparison for the properties between an offset transistor and an LDD transistor, and showed that an offset transistor acts as an effective protection unit against soft-breakdown leakage generated by a human body event.
Several of new processes have thus been developed recently. For example, the self-aligned silicide formation is the one which has attracted much attention in recent years for its practical application, e.g. it provides not only low-sheet resistance for SID regions and for gate electrode in MOS devices but also a very clean silicide-silicon interface. Besides, it reduces at least one mask count and no additional etching step is required other than that of the conventional silicided formation method.
Unfortunately, the device with a self-aligned silicided contact shows a worse electrostatic discharge (ESD) performance than the non-silicided devices. Amerasekera et al. in IEDM Tech. Dig. p.893 (1996), investigated the junction depth and the salicide thickness in a 0.25 .mu.m CMOS process affect the current gain .beta. of a self-biased lateral NPN (parasitic bipolar in aNMOS), and examined the relationship between .beta. and ESD performance, and proposed that the .beta. is observed to be strongly influenced by the effective drain/source diffusion depth below the salicide. The depth is determined by the implant energy as well as the amount of active diffusion consumed in silicidation. Thicker salicides are observed to reduce .beta.. Further, the lower .beta. is found to have lower ESD performance. Thus, one of the methodologies to solve the problems caused by the salicidation and the LDD is increasing the junction depth and removes the LDD structure in the ESD protective device when the ESD preventive circuitry and the ULSI devices with a salicidation are fabricated at the same time.
U.S. Pat. No. 4,717,684 to Katto et al., issued January 1988, describes a conventional method to fabricate an ESD circuit during the salicided process. As aforementioned, an ESD device is required to remove the LDD structure; thus, the process required several masks while forming the ESD protection devices and the MOSFET simultaneously. A modified process to reduce mask count was described in U.S. Pat. No. 5,672,527 to J. S. Lee, issued Sep. 1997. Lee proposed a new method to fabricate the ESD protection circuit and MOSFET at the same time. The features that Lee proposed are only one photo mask to form ESD protective circuits without the salicide and the LDD structure. However, the metal layer on the source/drain region of the ESD protection device is needs to be selectively etched before succeeding the silicides process as in his mentioned method. It is worth noting that it would be rather difficult to remove the metal layer on distinct material (e.g. silicon, oxide spacer, poly-silicon and isolation layer) without damaging the underlay substrate, and thus a complicated etching process is required.